1. Field of Invention
The present invention relates to power amplifiers and more particularly to multi-mode power amplifiers with improved linearity and reduced current consumption.
2. Description of Related Art
Power amplifiers are ubiquitous in modern electronics. There is a constant demand to decrease the power consumption and increase the linearity of power amplifiers in consumer electronic devices, especially portable devices. Conventional designs of power amplifiers focused on optimizing the power consumption and transmission characteristics for power outputs at the highest power-ranges.
However, a remarkable observation is represented by FIG. 2. The probability density function (PDF) of the usage of portable devices, such as cell phones, reveals that most of the time these devices are used at powers nowhere near the highest power-ranges. A key reason for this fact is that cell phones are typically in close proximity to the nearest base station. Therefore, the power of the output signal is far from their highest value. This observation poses new design challenges for power amplifiers.
One of these challenges is that power amplifiers have to amplify the received, or input, signals in a very broad range by the same factor. In other words, the output of power amplifiers has to be a linear function of its input over a broad power-range.
Another challenge is that power amplifiers, which were optimized for power output at the highest power-ranges consume unduly large currents at the typical lower power ranges.
Some existing designs address this problem by including two parallel-coupled output stage transistors, optimized for amplifying signals in a low power-range and in a high power-range. Signals with a typical power-range are routed through the low power output transistor, but when the signal's power-range increases to a high range, a bias-control circuit reconfigures the power amplifier by switching the signal route, or transmission path, through the high power output transistor.
Further, the signal, output from the parallel-coupled output stages, is coupled into an output impedance matching network to maximize power transfer to a standard 50 ohm system. In existing designs, there are separate output impedance matching networks coupled to the two parallel output transistors. When the signal route is changed from the low to the high power output transistor, a control circuit reconfigures the output impedance matching network as well by switching from the corresponding low power to the high power output impedance matching network.
However, these designs employ a switching element in the output transmission path. Such switching elements introduce non-linearities and losses into the transmission characteristics, occupying valuable chip area and requiring supply current.